Implementation of dynamic loop scheduling in reconfigurable platforms

Riakiotakis, I; Papakonstantinou, G; Chronopoulos, AT

dc.contributor.author	Riakiotakis, I	en
dc.contributor.author	Papakonstantinou, G	en
dc.contributor.author	Chronopoulos, AT	en
dc.date.accessioned	2014-03-01T02:45:30Z
dc.date.available	2014-03-01T02:45:30Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32282
dc.subject	Analytical Model	en
dc.subject	Case Study	en
dc.subject	Coarse Grained	en
dc.subject	Dynamic Scheduling	en
dc.subject	Loop Scheduling	en
dc.subject	Nested Loops	en
dc.subject	Parallel Computer	en
dc.subject	reconfigurable hardware	en
dc.subject	Processing Element	en
dc.subject.other	Computer networks	en
dc.subject.other	Computer programming languages	en
dc.subject.other	Data storage equipment	en
dc.subject.other	Integrated circuits	en
dc.subject.other	Parallel algorithms	en
dc.subject.other	Dynamic loop scheduling	en
dc.subject.other	International symposium	en
dc.subject.other	Embedded systems	en
dc.title	Implementation of dynamic loop scheduling in reconfigurable platforms	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/SIES.2008.4577675	en
heal.identifier.secondary	4577675	en
heal.identifier.secondary	http://dx.doi.org/10.1109/SIES.2008.4577675	en
heal.publicationDate	2008	en
heal.abstract	Dynamic scheduling algorithms have been successfully used for parallel computations of nested loops in traditional parallel computers and clusters. In this paper we propose a new architecture, implementing a coarse grain dynamic loop scheduling, suitable for reconfigurable hardware platforms. We use an analytical model and a case study to evaluate the performance of the proposed architecture. This approach makes efficient memory and processing elements use and thus gives better results than previous approaches. ©2008 IEEE.	en
heal.journalName	SIES'2008 - 3rd International Symposium on Industrial Embedded Systems	en
dc.identifier.doi	10.1109/SIES.2008.4577675	en
dc.identifier.spage	11	en
dc.identifier.epage	18	en