Mapping DSP applications onto high-performance architectural templates with inlined flexibility

Xydis, S; Economakos, G; Soudris, D; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:45:33Z
dc.date.available	2014-03-01T02:45:33Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32302
dc.subject	Coarse Grained	en
dc.subject	Design Technique	en
dc.subject	High Level Synthesis	en
dc.subject	High Performance	en
dc.subject	Intermediate Representation	en
dc.subject	reconfigurable architecture	en
dc.subject.other	Benchmark applications	en
dc.subject.other	Coarse-grained	en
dc.subject.other	Coarse-grained reconfigurable architectures	en
dc.subject.other	Data-paths	en
dc.subject.other	Design techniques	en
dc.subject.other	DSP applications	en
dc.subject.other	High-level specifications	en
dc.subject.other	Inlining	en
dc.subject.other	Intermediate representations	en
dc.subject.other	Mapping algorithms	en
dc.subject.other	Re-configurable	en
dc.subject.other	RTL implementation	en
dc.subject.other	Adaptive systems	en
dc.subject.other	Benchmarking	en
dc.subject.other	Digital signal processors	en
dc.subject.other	Standards	en
dc.subject.other	Conformal mapping	en
dc.title	Mapping DSP applications onto high-performance architectural templates with inlined flexibility	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/AHS.2008.20	en
heal.identifier.secondary	4584293	en
heal.identifier.secondary	http://dx.doi.org/10.1109/AHS.2008.20	en
heal.publicationDate	2008	en
heal.abstract	In this paper a formalized methodology is presented for mapping behavioral DSP kernels onto a novel reconfigurable architectural template. The architectural template is generated by a design technique called Flexibility Inlining, which delivers high performance coarse-grained reconfigurable architectures. The proposed methodology enables a seamless flow from high level specification to RTL implementation. A specialized intermediate representation model and a set of mapping algorithms have been considered to exploit the structure of the targeted architectures. Experimental results on DSP benchmark applications proves the efficiency of the proposed approach comparing with reconfigurable datapaths composed by standard coarse-grained cells. © 2008 IEEE.	en
heal.journalName	Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2008	en
dc.identifier.doi	10.1109/AHS.2008.20	en
dc.identifier.spage	346	en
dc.identifier.epage	353	en