A comparative study of blocking storage methods for sparse matrices on multicore architectures

Karakasis, V; Goumas, G; Koziris, N

dc.contributor.author	Karakasis, V	en
dc.contributor.author	Goumas, G	en
dc.contributor.author	Koziris, N	en
dc.date.accessioned	2014-03-01T02:45:51Z
dc.date.available	2014-03-01T02:45:51Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32435
dc.subject	Blocking	en
dc.subject	Performance evaluation	en
dc.subject	Sparse matrix-vector multiplication	en
dc.subject.other	Blocking performance	en
dc.subject.other	Comparative studies	en
dc.subject.other	Computational kernels	en
dc.subject.other	High demand	en
dc.subject.other	Indexing structures	en
dc.subject.other	Input matrices	en
dc.subject.other	Memory bandwidths	en
dc.subject.other	Memory subsystems	en
dc.subject.other	Micro architectures	en
dc.subject.other	Multicore architectures	en
dc.subject.other	Optimization techniques	en
dc.subject.other	Sparse matrices	en
dc.subject.other	Sparse matrix-vector multiplication	en
dc.subject.other	Storage formats	en
dc.subject.other	Online searching	en
dc.subject.other	Software architecture	en
dc.subject.other	Computational methods	en
dc.title	A comparative study of blocking storage methods for sparse matrices on multicore architectures	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/CSE.2009.223	en
heal.identifier.secondary	http://dx.doi.org/10.1109/CSE.2009.223	en
heal.identifier.secondary	5283031	en
heal.publicationDate	2009	en
heal.abstract	Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architecture. The main problem of SpMV is its high demands on memory bandwidth, which cannot yet be abudantly offered from modern commodity architectures. One of the most promising optimization techniques for SpMV is blocking, which can reduce the indexing structures for storing a sparse matrix, and therefore alleviate the pressure to the memory subsystem. In this paper, we study and evaluate a number of representative blocking storage formats on a set of modern microarchitectures that can provide up to 64 hardware contexts. The purpose of this paper is to present the merits and drawbacks of each method in relation to the underlying microarchitecture and to provide a consistent overview of the most promising blocking storage methods for sparse matrices that have been presented in the literature.	en
heal.journalName	Proceedings - 12th IEEE International Conference on Computational Science and Engineering, CSE 2009	en
dc.identifier.doi	10.1109/CSE.2009.223	en
dc.identifier.volume	1	en
dc.identifier.spage	247	en
dc.identifier.epage	256	en