A design methodology for high-performance and low-leakage fixed-point transpose FIR filters

Bekiaris, D; Xydis, S; Economatos, G; Pekmestzi, K

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Economatos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:45:52Z
dc.date.available	2014-03-01T02:45:52Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32437
dc.subject	Design Flow	en
dc.subject	Design Methodology	en
dc.subject	Fir Filter	en
dc.subject	Fixed Point	en
dc.subject	High Performance	en
dc.subject	Power Dissipation	en
dc.subject.other	Binary representations	en
dc.subject.other	Clock period	en
dc.subject.other	Design flows	en
dc.subject.other	Design Methodology	en
dc.subject.other	Level selection	en
dc.subject.other	Low leakage	en
dc.subject.other	Power dissipation	en
dc.subject.other	Standard-cell	en
dc.subject.other	Timing slack	en
dc.subject.other	FIR filters	en
dc.title	A design methodology for high-performance and low-leakage fixed-point transpose FIR filters	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2009.5410902	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2009.5410902	en
heal.identifier.secondary	5410902	en
heal.publicationDate	2009	en
heal.abstract	This paper addresse. The low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low- Vth Multiplication-Addition units by their high-Vth counterparts, taking into accoun. The timing slack of each unit an. The word-level binary representation oy the units coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69-25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation. © 2009 IEEE.	en
heal.journalName	2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009	en
dc.identifier.doi	10.1109/ICECS.2009.5410902	en
dc.identifier.spage	415	en
dc.identifier.epage	418	en