A formal method for rapid SoC prototyping

Pavlatos, C; Dimopoulos, AC; Papakonstantinou, G

dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Dimopoulos, AC	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:45:52Z
dc.date.available	2014-03-01T02:45:52Z
dc.date.issued	2009	en
dc.identifier.issn	10746005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32440
dc.subject	Attribute Grammar	en
dc.subject	Formal Method	en
dc.subject	Hardware Description Language	en
dc.subject	Hardware Implementation	en
dc.subject	Semantic Analysis	en
dc.subject.other	Attribute evaluation	en
dc.subject.other	Attribute grammars	en
dc.subject.other	Generic platforms	en
dc.subject.other	Hardware compilers	en
dc.subject.other	Hardware implementations	en
dc.subject.other	Hardware modules	en
dc.subject.other	Input string	en
dc.subject.other	Parsing algorithm	en
dc.subject.other	Prototyping	en
dc.subject.other	Semantic analysis	en
dc.subject.other	SoC implementation	en
dc.subject.other	Verilog hardware description languages	en
dc.subject.other	Verilog HDL	en
dc.subject.other	Context sensitive grammars	en
dc.subject.other	Formal methods	en
dc.subject.other	Hardware	en
dc.subject.other	Parallel algorithms	en
dc.subject.other	Programmable logic controllers	en
dc.subject.other	Specifications	en
dc.subject.other	Computer hardware description languages	en
dc.title	A formal method for rapid SoC prototyping	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/RSP.2009.25	en
heal.identifier.secondary	5158496	en
heal.identifier.secondary	http://dx.doi.org/10.1109/RSP.2009.25	en
heal.publicationDate	2009	en
heal.abstract	In this paper a formal method is proposed, based on Attribute Grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of Attribute Grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earley's parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesized in a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given. © 2009 IEEE.	en
heal.journalName	Proceedings of the International Workshop on Rapid System Prototyping	en
dc.identifier.doi	10.1109/RSP.2009.25	en
dc.identifier.spage	34	en
dc.identifier.epage	37	en