Flexible datapath synthesis through arithmetically optimized operation chaining

Xydis, S; Triantafyllou, I; Economakos, G; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Triantafyllou, I	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:46:10Z
dc.date.available	2014-03-01T02:46:10Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32579
dc.subject	Coarse Grained	en
dc.subject	Digital Signal Processing	en
dc.subject	High Level Synthesis	en
dc.subject	High Performance	en
dc.subject	Power Dissipation	en
dc.subject.other	Application domains	en
dc.subject.other	Architectural levels	en
dc.subject.other	Chip areas	en
dc.subject.other	Complex operations	en
dc.subject.other	Data paths	en
dc.subject.other	Execution time	en
dc.subject.other	High performance architectures	en
dc.subject.other	Optimized operations	en
dc.subject.other	Power dissipation	en
dc.subject.other	Proposed architectures	en
dc.subject.other	Synthesis methodology	en
dc.subject.other	Template-based	en
dc.subject.other	Digital signal processors	en
dc.subject.other	Signal processing	en
dc.subject.other	Optimization	en
dc.title	Flexible datapath synthesis through arithmetically optimized operation chaining	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/AHS.2009.21	en
heal.identifier.secondary	http://dx.doi.org/10.1109/AHS.2009.21	en
heal.identifier.secondary	5325425	en
heal.publicationDate	2009	en
heal.abstract	Datapath synthesis incorporating complex operation templates has been proven extremely efficient especially for the Digital Signal Processing (DSP) application domain. However, only architectural level optimizations have been reported for the specification and implementation of the operation templates. This paper introduces the consideration of arithmetic level optimizations for template based datapath synthesis. A high performance architecture for the implementation of DSP kernels is presented. It is based on flexible and arithmetically optimized components able to perform a large set of operation templates. A synthesis methodology for optimized mapping of DSP kernels onto the proposed architecture is also presented. Experimental results are reported showing significant gains in execution time, active chip area and power dissipation in comparison to previously published flexible template-based datapaths. © 2009 IEEE.	en
heal.journalName	Proceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009	en
dc.identifier.doi	10.1109/AHS.2009.21	en
dc.identifier.spage	407	en
dc.identifier.epage	414	en