High-level synthesis with coarse grain reconfigurable components

Economakos, G; Xydis, S

dc.contributor.author	Economakos, G	en
dc.contributor.author	Xydis, S	en
dc.date.accessioned	2014-03-01T02:46:11Z
dc.date.available	2014-03-01T02:46:11Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32591
dc.subject	Coarse Grained	en
dc.subject	Critical Path	en
dc.subject	High Level Synthesis	en
dc.subject.other	Coarse-grain reconfigurable	en
dc.subject.other	Critical Paths	en
dc.subject.other	Data paths	en
dc.subject.other	Different modes	en
dc.subject.other	DSP benchmarks	en
dc.subject.other	High Level Synthesis	en
dc.subject.other	Performance Gain	en
dc.subject.other	Post-processor	en
dc.subject.other	Reconfiguration overhead	en
dc.subject.other	Synthesis methodology	en
dc.subject.other	Frequency multiplying circuits	en
dc.subject.other	Distributed parameter networks	en
dc.title	High-level synthesis with coarse grain reconfigurable components	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IPDPS.2009.5161216	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IPDPS.2009.5161216	en
heal.identifier.secondary	5161216	en
heal.publicationDate	2009	en
heal.abstract	High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in highlevel synthesis. The gate-level synthesis methodology for this component imposes practically no extra hardware than a normal multiplier while involvement in high-level synthesis is performed with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of almost 70% with a 45% datapath area gain. © 2009 IEEE.	en
heal.journalName	IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium	en
dc.identifier.doi	10.1109/IPDPS.2009.5161216	en