Node resource management for dsp applications on 3D network-on-chip architecture

Anagnostopoulos, I; Bartzas, A; Vourkas, I; Soudris, D

dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Vourkas, I	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:46:14Z
dc.date.available	2014-03-01T02:46:14Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32625
dc.subject	3D integrated circuits	en
dc.subject	DSP applications	en
dc.subject	Network-on-chip	en
dc.subject	Quality-of-service	en
dc.subject.other	3D integrated circuits	en
dc.subject.other	3D meshes	en
dc.subject.other	3D networks	en
dc.subject.other	Buffer sizing	en
dc.subject.other	Buffer space	en
dc.subject.other	Complex applications	en
dc.subject.other	DSP application	en
dc.subject.other	DSP applications	en
dc.subject.other	Intellectual property cores	en
dc.subject.other	IP core	en
dc.subject.other	Latency constraints	en
dc.subject.other	Network-on-chip	en
dc.subject.other	Network-on-chip architectures	en
dc.subject.other	NoC architectures	en
dc.subject.other	Priority assignment	en
dc.subject.other	Resource management	en
dc.subject.other	Resource management techniques	en
dc.subject.other	Systematic designs	en
dc.subject.other	Biological materials	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Digital signal processors	en
dc.subject.other	Electric network topology	en
dc.subject.other	Integrated circuits	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Internet protocols	en
dc.subject.other	Natural resources management	en
dc.subject.other	Network architecture	en
dc.subject.other	Network management	en
dc.subject.other	Quality of service	en
dc.subject.other	Resource allocation	en
dc.subject.other	Signal processing	en
dc.subject.other	Three dimensional	en
dc.subject.other	Routers	en
dc.title	Node resource management for dsp applications on 3D network-on-chip architecture	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICDSP.2009.5201090	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICDSP.2009.5201090	en
heal.identifier.secondary	5201090	en
heal.publicationDate	2009	en
heal.abstract	Emerging DSP applications have different latency, energy onsumption and Quality of Service (QoS) requirements. An implementation of such applications requires a large number of intellectual property (IP) cores, communicating with each other, meeting the energy and latency constraints. Networkon-Chip (NoC) architectures is able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. This leads to different usage of the available buffer space in the routers of the NoC system. In this work we propose power and the systematic design of novel NOC-based architectures, which realize DSP applications. Additionally, we present an integrated node resource management technique that combines priority assignment and buffer sizing so that the NoC system to best serve requirements of the considered Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time. DSP applications. The proposed approach has been evaluated both on 2D and 3D mesh topologies by employing an NoC simulator and four real DSP/multimedia applications gaining an average of 34% on energyxdelay product for each application. Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time. © 2009 IEEE.	en
heal.journalName	DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings	en
dc.identifier.doi	10.1109/ICDSP.2009.5201090	en