Optimized reconfigurable RTL components for performance improvements during high-level synthesis

Economakos, G; Xydis, S

dc.contributor.author	Economakos, G	en
dc.contributor.author	Xydis, S	en
dc.date.accessioned	2014-03-01T02:46:17Z
dc.date.available	2014-03-01T02:46:17Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32639
dc.subject	Coarse grain reconfigurable components	en
dc.subject	High-level synthesis	en
dc.subject	Reconfigurable computing	en
dc.subject	Run time reconfiguration	en
dc.subject.other	Coarse-grain reconfigurable	en
dc.subject.other	Critical Paths	en
dc.subject.other	Data paths	en
dc.subject.other	Different modes	en
dc.subject.other	DSP benchmarks	en
dc.subject.other	High Level Synthesis	en
dc.subject.other	Performance Gain	en
dc.subject.other	Performance improvements	en
dc.subject.other	Post-processor	en
dc.subject.other	Re-configurable	en
dc.subject.other	Reconfigurable computing	en
dc.subject.other	Reconfiguration overhead	en
dc.subject.other	Run time reconfiguration	en
dc.subject.other	Synthesis methodology	en
dc.subject.other	Frequency multiplying circuits	en
dc.title	Optimized reconfigurable RTL components for performance improvements during high-level synthesis	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DSD.2009.193	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DSD.2009.193	en
heal.identifier.secondary	5350117	en
heal.publicationDate	2009	en
heal.abstract	High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology proposed for this component imposes practically no extra hardware than a normal multiplier, as shown after extensive experimentation. Involvement in high-level synthesis is performed with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15% without practically any datapath area increase. © 2009 IEEE.	en
heal.journalName	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009	en
dc.identifier.doi	10.1109/DSD.2009.193	en
dc.identifier.spage	164	en
dc.identifier.epage	171	en