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Overlapping computation and communication in SMT clusters with commodity interconnects

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dc.contributor.author Goumas, G en
dc.contributor.author Anastopoulos, N en
dc.contributor.author Koziris, N en
dc.contributor.author Ioannou, N en
dc.date.accessioned 2014-03-01T02:46:17Z
dc.date.available 2014-03-01T02:46:17Z
dc.date.issued 2009 en
dc.identifier.issn 15525244 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/32642
dc.subject Overlapping en
dc.subject SMT architecture en
dc.subject.other Advection equations en
dc.subject.other Gbit Ethernet en
dc.subject.other Helper threading en
dc.subject.other Overlapping en
dc.subject.other Performance improvements en
dc.subject.other Simultaneous multithreading processors en
dc.subject.other Test case en
dc.subject.other Cluster computing en
dc.subject.other Computer science en
dc.subject.other Ethernet en
dc.subject.other Technical presentations en
dc.subject.other Multitasking en
dc.title Overlapping computation and communication in SMT clusters with commodity interconnects en
heal.type conferenceItem en
heal.identifier.primary 10.1109/CLUSTR.2009.5289174 en
heal.identifier.secondary http://dx.doi.org/10.1109/CLUSTR.2009.5289174 en
heal.identifier.secondary 5289174 en
heal.publicationDate 2009 en
heal.abstract In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethernet), by applying overlapping of computation with communication. As a test case we consider the parallelized advection equation and discuss the steps that need to be followed to semantically allow overlapping to occur.We propose an implementation based on the concept of Helper Threading that distributes computation and communication in the two sibling threads of an SMT processor, thus creating an asymmetric pair of execution patterns in each hardware context. Our experimental results in an 8-node cluster interconnected with commodity Gbit Ethernet demonstrate that the proposed implementation is able to achieve substantial performance improvements that can exceed 20% in some cases, by efficiently utilizing the available resources of the SMT processors. ©2009 IEEE. en
heal.journalName Proceedings - IEEE International Conference on Cluster Computing, ICCC en
dc.identifier.doi 10.1109/CLUSTR.2009.5289174 en


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