Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Siozios, K; Soudris, D; Economakos, G

dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T02:46:33Z
dc.date.available	2014-03-01T02:46:33Z
dc.date.issued	2009	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32712
dc.subject	3D architecture	en
dc.subject	DSP	en
dc.subject	FPGA	en
dc.subject	Integration	en
dc.subject	Interconnection	en
dc.subject.other	3D architecture	en
dc.subject.other	Clock frequency	en
dc.subject.other	Comparison result	en
dc.subject.other	Design parameters	en
dc.subject.other	Design technologies	en
dc.subject.other	Digital system	en
dc.subject.other	DSP	en
dc.subject.other	DSP application	en
dc.subject.other	DSP implementation	en
dc.subject.other	Emerging technologies	en
dc.subject.other	FPGA	en
dc.subject.other	FPGA architectures	en
dc.subject.other	FPGA devices	en
dc.subject.other	Hardware resources	en
dc.subject.other	Interconnection	en
dc.subject.other	Logic density	en
dc.subject.other	Modern applications	en
dc.subject.other	New design	en
dc.subject.other	Number of layers	en
dc.subject.other	Performance improvements	en
dc.subject.other	Power Consumption	en
dc.subject.other	Process Technologies	en
dc.subject.other	Proposed architectures	en
dc.subject.other	Silicon area	en
dc.subject.other	Three dimensional (3D) integration	en
dc.subject.other	Three-dimensional FPGA	en
dc.subject.other	Design	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Electric power utilization	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Signal processing	en
dc.subject.other	Software architecture	en
dc.subject.other	Three dimensional	en
dc.subject.other	Digital signal processors	en
dc.title	Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICDSP.2009.5201124	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICDSP.2009.5201124	en
heal.identifier.secondary	5201124	en
heal.publicationDate	2009	en
heal.abstract	Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important when we deal with Digital System Processor (DSP) kernels, as there are demands for even higher clock frequencies and logic densities, which cannot be satisfied with existing design technologies. Three-dimensional (3D) integration is an emerging technology that promises to alleviate problems related to performance improvement, but up to now this new design approach has not been sufficiently explored. In this paper we propose a novel 3D FPGA architecture able to implement efficiently DSP applications. The proposed architecture is software-supported by a methodology targeting to explore DSP enhanced 3D FPGA devices. During our study we quantify a number of design parameters, such as the selected number of layers, the proper bonding approach, the process technology for each layer, etc. Comparison results prove the efficiency (in terms of performance and power consumption) of the new design paradigm, as compared to existing commercial devices with similar hardware resources. © 2009 IEEE.	en
heal.journalName	DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings	en
dc.identifier.doi	10.1109/ICDSP.2009.5201124	en