A bit level area aware cache-based architecture for memory repairs

Axelos, N; Pekmestzi, K

dc.contributor.author	Axelos, N	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:46:35Z
dc.date.available	2014-03-01T02:46:35Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32736
dc.subject	Defect Density	en
dc.subject	Built In Self Repair	en
dc.subject.other	Area savings	en
dc.subject.other	Bit level	en
dc.subject.other	Built-in self-repair	en
dc.subject.other	Cache-based architectures	en
dc.subject.other	High defect densities	en
dc.subject.other	Memory repair	en
dc.subject.other	Modified scheme	en
dc.subject.other	Repairability	en
dc.subject.other	Word level	en
dc.subject.other	Architecture	en
dc.subject.other	Cache memory	en
dc.subject.other	Repair	en
dc.title	A bit level area aware cache-based architecture for memory repairs	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IOLTS.2010.5560217	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IOLTS.2010.5560217	en
heal.identifier.secondary	5560217	en
heal.publicationDate	2010	en
heal.abstract	In this paper an architecture for memory Built-In Self-Repair (BISR) is presented. The proposed scheme utilises a multiple bank cache-like memory for repairing defective bits and is a heavily modified version of a previously studied architecture that repaired at the word level, while the proposed repairs at the bit level. This scheme achieves high repair ratios at high defect densities with small overheads. The two architectures are compared on their footprint by means of an area approximation analysis. The proposed modified scheme shows significant area savings (greater than 4 times) while retaining the same high repairability qualities as its predecessor. © 2010 IEEE.	en
heal.journalName	Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010	en
dc.identifier.doi	10.1109/IOLTS.2010.5560217	en
dc.identifier.spage	154	en
dc.identifier.epage	158	en