A fast multiplier-less edge detection accelerator for FPGAs

Anastasiadis, N; Sideris, I; Pekmestzi, K

dc.contributor.author	Anastasiadis, N	en
dc.contributor.author	Sideris, I	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:46:35Z
dc.date.available	2014-03-01T02:46:35Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32741
dc.subject	coprocessor	en
dc.subject	edge detection	en
dc.subject	FPGA	en
dc.subject	FSL	en
dc.subject.other	A-frames	en
dc.subject.other	Block rams	en
dc.subject.other	Co-processors	en
dc.subject.other	coprocessor	en
dc.subject.other	Fast multipliers	en
dc.subject.other	Frame rate	en
dc.subject.other	Frames per seconds	en
dc.subject.other	High resolution	en
dc.subject.other	Processing power	en
dc.subject.other	Processing Time	en
dc.subject.other	Real time performance	en
dc.subject.other	Real time videos	en
dc.subject.other	Video surveillance	en
dc.subject.other	Xilinx spartan-3	en
dc.subject.other	Medical imaging	en
dc.subject.other	Radar absorbing materials	en
dc.subject.other	Security systems	en
dc.subject.other	Edge detection	en
dc.title	A fast multiplier-less edge detection accelerator for FPGAs	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1774088.1774193	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1774088.1774193	en
heal.publicationDate	2010	en
heal.abstract	Real time video is used in a wide variety of applications, ranging from video surveillance to medical imaging. These operations require significant amounts of processing power, especially when high resolution frames are used. A large percentage of processing time is used in edge detection kernels. Thus, accelerating these kernels is of vital importance in achieving satisfactory frame rates for real time performance, even in high resolutions. This paper proposes a hardware coprocessor to the Xilinx Microblaze processor which accelerates edge detection significantly, while keeping the hardware requirements low, by using no multipliers at all. Using a Xilinx Spartan 3E FPGA, we have reported a frame rate of 157 frames per second in 4CIF format, which corresponds to a 4x speedup over the software only solution. The speedup was achieved with only 1131 slices and 5 block RAMs hardware occupation, which makes the solution very attractable. © 2010 ACM.	en
heal.journalName	Proceedings of the ACM Symposium on Applied Computing	en
dc.identifier.doi	10.1145/1774088.1774193	en
dc.identifier.spage	510	en
dc.identifier.epage	515	en