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A high-level mapping algorithm targeting 3D NoC architectures with multiple Vdd

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dc.contributor.author Siozios, K en
dc.contributor.author Anagnostopoulos, I en
dc.contributor.author Soudris, D en
dc.date.accessioned 2014-03-01T02:46:36Z
dc.date.available 2014-03-01T02:46:36Z
dc.date.issued 2010 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/32747
dc.subject Energy Saving en
dc.subject Low Power en
dc.subject Real Time en
dc.subject.other Communication problems en
dc.subject.other Delay overheads en
dc.subject.other Energy saving en
dc.subject.other Level mapping en
dc.subject.other Low Power en
dc.subject.other Multiple VDD en
dc.subject.other NoC architectures en
dc.subject.other Supply voltages en
dc.subject.other Temperature reduction en
dc.subject.other Communication en
dc.subject.other Conformal mapping en
dc.subject.other Energy conservation en
dc.subject.other Three dimensional en
dc.title A high-level mapping algorithm targeting 3D NoC architectures with multiple Vdd en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ISVLSI.2010.98 en
heal.identifier.secondary http://dx.doi.org/10.1109/ISVLSI.2010.98 en
heal.identifier.secondary 5572834 en
heal.publicationDate 2010 en
heal.abstract The communication problem in modern ICs becomes a challenge Issue. This paper introduces a high-level mapping algorithm targeting to low-power 3D NoC devices. By appropriately assigning application's functionalities to layers with different supply voltages we achieve reasonable energy savings and temperature reduction. Additionally, our methodology supports real-time adaption on different traffic scenarios. Experimental results show that energy savings up to 19% are feasible, without any area and delay overhead, as compared to architectures powered by only one supply voltage. © 2010 IEEE. en
heal.journalName Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 en
dc.identifier.doi 10.1109/ISVLSI.2010.98 en
dc.identifier.spage 444 en
dc.identifier.epage 445 en


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