A mixed style architecture for low power multipliers based on a bypass technique

Economakos, G; Bekiaris, D; Pekmestzi, K

dc.contributor.author	Economakos, G	en
dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:46:38Z
dc.date.available	2014-03-01T02:46:38Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32751
dc.subject	Data gating	en
dc.subject	Digital multipliers	en
dc.subject	Dynamic power	en
dc.subject	Low-power design	en
dc.subject	Transmission gates	en
dc.subject.other	Data gating	en
dc.subject.other	Digital multiplier	en
dc.subject.other	Dynamic power	en
dc.subject.other	Low-power design	en
dc.subject.other	Transmission gates	en
dc.subject.other	Architecture	en
dc.subject.other	Design	en
dc.subject.other	Electric power supplies to apparatus	en
dc.subject.other	Integrated control	en
dc.subject.other	Nanostructured materials	en
dc.subject.other	Multiplying circuits	en
dc.title	A mixed style architecture for low power multipliers based on a bypass technique	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DTIS.2010.5487585	en
heal.identifier.secondary	5487585	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DTIS.2010.5487585	en
heal.publicationDate	2010	en
heal.abstract	In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption. While this idea offers great savings mainly to array multipliers, due to their regular interconnection scheme, the reduced area and fast speed of tree multipliers is a real temptation for the designer. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that the bypass technique offers minimum power consumption for all cases while the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. © 2010 IEEE.	en
heal.journalName	5th Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2010	en
dc.identifier.doi	10.1109/DTIS.2010.5487585	en