A mixed style multiplier architecture for low dynamic and leakage power dissipation

Bekiaris, D; Economakos, G; Pekmestzi, K

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:46:38Z
dc.date.available	2014-03-01T02:46:38Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32752
dc.subject	combinational circuit	en
dc.subject	Leakage Power	en
dc.subject	Low Power	en
dc.subject	Power Consumption	en
dc.subject	Power Saving	en
dc.subject.other	Area overhead	en
dc.subject.other	Array multipliers	en
dc.subject.other	Basic idea	en
dc.subject.other	Combinational circuits	en
dc.subject.other	Deep sub-micron technology	en
dc.subject.other	Dynamic Power	en
dc.subject.other	Dynamic power consumption	en
dc.subject.other	Leakage power	en
dc.subject.other	Low delay	en
dc.subject.other	Low leakage	en
dc.subject.other	Low Power	en
dc.subject.other	Multiplier architecture	en
dc.subject.other	Power products	en
dc.subject.other	Timing slack	en
dc.subject.other	Transmission gate	en
dc.subject.other	Tree multiplier	en
dc.subject.other	Tree-based	en
dc.subject.other	Architecture	en
dc.subject.other	Design	en
dc.subject.other	Multiplying circuits	en
dc.title	A mixed style multiplier architecture for low dynamic and leakage power dissipation	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/VDAT.2010.5496738	en
heal.identifier.secondary	http://dx.doi.org/10.1109/VDAT.2010.5496738	en
heal.identifier.secondary	5496738	en
heal.publicationDate	2010	en
heal.abstract	In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and fast speed advantages of tree multipliers. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that while the bypass technique offers the minimum dynamic power consumption value, the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. Furthermore, the tree part of the mixed architecture has enough timing slack to be implemented with high Vth low leakage components, offering an extra 20%-30% leakage power saving, which is a considerable value in deep submicron technologies. ©2010 IEEE.	en
heal.journalName	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010	en
dc.identifier.doi	10.1109/VDAT.2010.5496738	en
dc.identifier.spage	258	en
dc.identifier.epage	261	en