A new low-power soft-error tolerant SRAM cell

Axelos, N; Pekmestzit, K; Moschopoulos, N

dc.contributor.author	Axelos, N	en
dc.contributor.author	Pekmestzit, K	en
dc.contributor.author	Moschopoulos, N	en
dc.date.accessioned	2014-03-01T02:46:38Z
dc.date.available	2014-03-01T02:46:38Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32754
dc.subject	Leakage Current	en
dc.subject	Low Power	en
dc.subject	Power Consumption	en
dc.subject	Soft Error	en
dc.subject.other	6T-cell	en
dc.subject.other	6T-SRAM	en
dc.subject.other	90 nm technology	en
dc.subject.other	CMOS technology	en
dc.subject.other	Error tolerant	en
dc.subject.other	Guard-gates	en
dc.subject.other	Low Power	en
dc.subject.other	Soft error	en
dc.subject.other	SRAM Cell	en
dc.subject.other	Static power consumption	en
dc.subject.other	CMOS integrated circuits	en
dc.subject.other	Static random access storage	en
dc.title	A new low-power soft-error tolerant SRAM cell	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISVLSI.2010.83	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISVLSI.2010.83	en
heal.identifier.secondary	5572816	en
heal.publicationDate	2010	en
heal.abstract	In this paper we present a new 12T loadless SRAM cell that exhibits soft error resilience characteristics. The proposed cell is based on an interlocked structure with guard gates that provides an ×80 increase in soft error resilience compared to a typical unprotected 6T SRAM cell, while addressing the static power consumption issue of modern CMOS technologies. At a 90nm technology, simulations show that the investigated 12T SRAM cell draws 3 times less leakage current than a DICE cell of similarly sized transistors and 20% less than a typical 6T cell. © 2010 IEEE.	en
heal.journalName	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010	en
dc.identifier.doi	10.1109/ISVLSI.2010.83	en
dc.identifier.spage	399	en
dc.identifier.epage	404	en