Bit-width exploration over 3D architectures using high-level synthesis

Koutras, I; Papanikolaou, A; Economakos, G; Soudris, D

dc.contributor.author	Koutras, I	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:46:42Z
dc.date.available	2014-03-01T02:46:42Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32797
dc.subject	Design automation	en
dc.subject	High-level synthesis	en
dc.subject.other	3D architectures	en
dc.subject.other	3D stacking technology	en
dc.subject.other	Bit-Width	en
dc.subject.other	Complete system	en
dc.subject.other	Design automations	en
dc.subject.other	Embedded system design	en
dc.subject.other	High-level synthesis	en
dc.subject.other	Interface circuitry	en
dc.subject.other	Memory interface	en
dc.subject.other	Power efficiency	en
dc.subject.other	Processing elements	en
dc.subject.other	State-of-the-art system	en
dc.subject.other	Computer aided design	en
dc.subject.other	Embedded software	en
dc.subject.other	Systems analysis	en
dc.subject.other	Three dimensional	en
dc.subject.other	Energy efficiency	en
dc.title	Bit-width exploration over 3D architectures using high-level synthesis	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2010.5724567	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2010.5724567	en
heal.identifier.secondary	5724567	en
heal.publicationDate	2010	en
heal.abstract	The interface between storage and processing has always been one of the main bottlenecks to the performance and energy efficiency in embedded system design. In this paper we are exploring the potential to increase the bandwidth through this interface by increasing the number of physical connections. This option becomes available using 3D stacking technologies. Our aim is to evaluate the power efficiency of a wider memory interface at the level of the complete system, including the memory, the interface circuitry itself and the processing elements. We want to understand whether this additional bandwidth can be efficiently utilized by the processing elements and enable an overall lower power and higher throughput solution compared to state-of-the-art system implementations. ©2010 IEEE.	en
heal.journalName	2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings	en
dc.identifier.doi	10.1109/ICECS.2010.5724567	en
dc.identifier.spage	535	en
dc.identifier.epage	538	en