Construction of dual mode components for reconfiguration aware high-level synthesis

Economakos, G; Xydis, S; Koutras, I; Soudris, D

dc.contributor.author	Economakos, G	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Koutras, I	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:46:43Z
dc.date.available	2014-03-01T02:46:43Z
dc.date.issued	2010	en
dc.identifier.issn	15301591	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32811
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-77953116647&partnerID=40&md5=bc71016f22dd41b6fdf71bee99c677d3	en
dc.relation.uri	http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05457021	en
dc.relation.uri	http://portal.acm.org/citation.cfm?id=1871252	en
dc.relation.uri	http://portal.acm.org/ft_gateway.cfm?id=1871252&type=pdf&CFID=29576336&CFTOKEN=51534192	en
dc.relation.uri	http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457021	en
dc.relation.uri	http://www.informatik.uni-trier.de/~ley/db/conf/date/date2010.html#EconomakosXKS10	en
dc.subject	Coarse grained reconfigurable components	en
dc.subject	High-level synthesis	en
dc.subject	Reconfigurable computing	en
dc.subject	Scheduling	en
dc.subject.other	Alternative approach	en
dc.subject.other	Coarse-grained	en
dc.subject.other	Critical Paths	en
dc.subject.other	Data paths	en
dc.subject.other	Different modes	en
dc.subject.other	DSP benchmarks	en
dc.subject.other	Dual modes	en
dc.subject.other	Exhaustive search	en
dc.subject.other	High Level Synthesis	en
dc.subject.other	Industrial acceptance	en
dc.subject.other	Performance Gain	en
dc.subject.other	Quality of results	en
dc.subject.other	Reconfigurable components	en
dc.subject.other	Reconfigurable computing	en
dc.subject.other	Reconfiguration overhead	en
dc.subject.other	Resource utilizations	en
dc.subject.other	Multiobjective optimization	en
dc.subject.other	Scheduling	en
dc.subject.other	Synthesis (chemical)	en
dc.title	Construction of dual mode components for reconfiguration aware high-level synthesis	en
heal.type	conferenceItem	en
heal.identifier.secondary	5457021	en
heal.publicationDate	2010	en
heal.abstract	High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area lately addressed is reconfigurable computing, where parts of a DFG are merged and mapped into coarse grained reconfigurable components. This paper presents an alternative approach, the construction of dual mode components which are exchanged with regular components in the resulting RTL architecture. The dual mode components are constructed by exhaustive search for dual mode functional primitives inside the datapath of complicated RTL components. Such components, like multipliers and dividers, that would remain idle in certain control steps, are able to work full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization. © 2010 EDAA.	en
heal.journalName	Proceedings -Design, Automation and Test in Europe, DATE	en
dc.identifier.spage	1357	en
dc.identifier.epage	1360	en