dc.contributor.author |
Xydis, S |
en |
dc.contributor.author |
Skouroumounis, C |
en |
dc.contributor.author |
Pekmestzi, K |
en |
dc.contributor.author |
Soudris, D |
en |
dc.contributor.author |
Economakos, G |
en |
dc.date.accessioned |
2014-03-01T02:46:46Z |
|
dc.date.available |
2014-03-01T02:46:46Z |
|
dc.date.issued |
2010 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32838 |
|
dc.subject |
Design Space |
en |
dc.subject |
Design Space Exploration |
en |
dc.subject |
High Level Synthesis |
en |
dc.subject.other |
Data paths |
en |
dc.subject.other |
Design spaces |
en |
dc.subject.other |
Efficient designs |
en |
dc.subject.other |
Exploration methods |
en |
dc.subject.other |
Globaloptimum |
en |
dc.subject.other |
Gradient based |
en |
dc.subject.other |
High Level Synthesis |
en |
dc.subject.other |
Level transformation |
en |
dc.subject.other |
Pruning techniques |
en |
dc.subject.other |
Quality design |
en |
dc.subject.other |
Quality of design |
en |
dc.subject.other |
Runtimes |
en |
dc.subject.other |
Second level |
en |
dc.subject.other |
Solution space |
en |
dc.subject.other |
Space research |
en |
dc.subject.other |
Design |
en |
dc.title |
Efficient high level synthesis exploration methodology combining exhaustive and gradient-based pruned searching |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/ISVLSI.2010.56 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/ISVLSI.2010.56 |
en |
heal.identifier.secondary |
5571801 |
en |
heal.publicationDate |
2010 |
en |
heal.abstract |
This paper presents a methodology for fast and efficient Design Space Exploration during High Level Synthesis. An augmented instance of the design space is studied taking under consideration the effects of both compiler- and architectural-level transformations onto the final datapath. A new gradient-based pruning technique has been developed, which evaluates large portions of the augmented solution space in a quick manner. At a second level, the proposed pruning technique is combined with exhaustive exploration in order to guarantee the quality of design solutions. We show that the proposed methodology delivers (I) higher quality designs than exploration methods which do not account the introduced extended design space, (ii) with considerable reductions of the exploration's runtime and (iii) efficient convergence to global optima. © 2010 IEEE. |
en |
heal.journalName |
Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 |
en |
dc.identifier.doi |
10.1109/ISVLSI.2010.56 |
en |
dc.identifier.spage |
104 |
en |
dc.identifier.epage |
109 |
en |