Multiple Vddon 3D NoC architectures

Siozios, K; Anagnostopoulos, I; Soudris, D

dc.contributor.author	Siozios, K	en
dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:46:53Z
dc.date.available	2014-03-01T02:46:53Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32915
dc.subject	Multiple Vdd	en
dc.subject	Network-on-Chip	en
dc.subject	Voltage scaling	en
dc.subject.other	Application mapping	en
dc.subject.other	Communication problems	en
dc.subject.other	Design approaches	en
dc.subject.other	Energy saving	en
dc.subject.other	IP core	en
dc.subject.other	Multiple V <sub>dd</sub>	en
dc.subject.other	Network-on-Chip	en
dc.subject.other	NoC architectures	en
dc.subject.other	Performance improvements	en
dc.subject.other	Power efficient	en
dc.subject.other	Temperature reduction	en
dc.subject.other	Three dimensional integration	en
dc.subject.other	Timing constraints	en
dc.subject.other	Voltage scaling	en
dc.subject.other	Communication	en
dc.subject.other	Energy conservation	en
dc.subject.other	Servers	en
dc.subject.other	Three dimensional	en
dc.subject.other	Timing circuits	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Routers	en
dc.title	Multiple Vddon 3D NoC architectures	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2010.5724641	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2010.5724641	en
heal.identifier.secondary	5724641	en
heal.publicationDate	2010	en
heal.abstract	The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-dimensional integration (3D), as well as network-on-chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for power-efficient application mapping onto 3D NoC-based devices. By clustering into the same router, IP cores with similar communication demands it is possible to achieve reasonable energy savings while meeting timing constraints. Experimental results prove the efficiency of the proposed methodology since we achieve energy savings and temperature reduction up to 19% and 11%, respectively. ©2010 IEEE.	en
heal.journalName	2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings	en
dc.identifier.doi	10.1109/ICECS.2010.5724641	en
dc.identifier.spage	831	en
dc.identifier.epage	834	en