Systematic exploration of energy-efficient application-specific network-on-chip architectures

Filippopoulos, I; Anagnostopoulos, I; Bartzas, A; Soudris, D; Economakos, G

dc.contributor.author	Filippopoulos, I	en
dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T02:47:05Z
dc.date.available	2014-03-01T02:47:05Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32992
dc.subject	Energy Efficient	en
dc.subject	Multimedia Application	en
dc.subject	Network On Chip	en
dc.subject	System On Chip	en
dc.subject.other	Adaptiveness	en
dc.subject.other	Application partitioning	en
dc.subject.other	Application-Specific	en
dc.subject.other	Application-specific network	en
dc.subject.other	Automatic topology	en
dc.subject.other	Complex applications	en
dc.subject.other	Energy aware	en
dc.subject.other	Energy efficient	en
dc.subject.other	Energy reduction	en
dc.subject.other	IP core	en
dc.subject.other	Network on chip	en
dc.subject.other	New system	en
dc.subject.other	NoC architectures	en
dc.subject.other	On-chip interconnection	en
dc.subject.other	Systematic exploration	en
dc.subject.other	Systematic methodology	en
dc.subject.other	Application specific integrated circuits	en
dc.subject.other	Computer architecture	en
dc.subject.other	Network architecture	en
dc.subject.other	Servers	en
dc.subject.other	Topology	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Routers	en
dc.title	Systematic exploration of energy-efficient application-specific network-on-chip architectures	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISVLSI.2010.60	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISVLSI.2010.60	en
heal.identifier.secondary	5572759	en
heal.publicationDate	2010	en
heal.abstract	Network-on-Chip (NoC), a new System-on-Chip paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Especially, custom NoC topologies are able to further increase application's performance due to their adaptiveness. In this paper, we present a systematic methodology for generating an energyefficient application-specific NoC architecture. The methodology framework consists of the following steps: 1) greedy application partitioning; 2) automatic topology generation and extensive exploration; and 3) an energy-aware router optimization so as to find the best architecture that meets applications requirements. Validation of the proposed framework was performed using four DSP/multimedia applications showing that energy-aware irregular NoCs can achieve on average 53% energy reduction, without violating applications timing constrains. © 2010 IEEE.	en
heal.journalName	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010	en
dc.identifier.doi	10.1109/ISVLSI.2010.60	en
dc.identifier.spage	133	en
dc.identifier.epage	138	en