A framework for architecture-level exploration of communication intensive applications onto 3-D FPGAs

Sidiropoulos, H; Siozios, K; Soudris, D

dc.contributor.author	Sidiropoulos, H	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:47:13Z
dc.date.available	2014-03-01T02:47:13Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33024
dc.subject	Consumer Electronics	en
dc.subject	Power Consumption	en
dc.subject	Power Dissipation	en
dc.subject	Three Dimensional	en
dc.subject.other	3D architectures	en
dc.subject.other	Application mapping	en
dc.subject.other	Area overhead	en
dc.subject.other	Chip stacking	en
dc.subject.other	Consumer electronics products	en
dc.subject.other	Delay reduction	en
dc.subject.other	FPGA devices	en
dc.subject.other	Integration technologies	en
dc.subject.other	Interconnection structure	en
dc.subject.other	Supporting tool	en
dc.subject.other	Two layers	en
dc.subject.other	Consumer electronics	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Three dimensional	en
dc.title	A framework for architecture-level exploration of communication intensive applications onto 3-D FPGAs	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/FPL.2011.109	en
heal.identifier.secondary	http://dx.doi.org/10.1109/FPL.2011.109	en
heal.identifier.secondary	6044780	en
heal.publicationDate	2011	en
heal.abstract	The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moores momentum and fuel the next wave of consumer electronics products. However, the benefits of such an integration technology have not been sufficiently explored yet. In this paper, we introduce a novel 3-D architecture, as well as the software supporting tools for exploring and evaluating application mapping onto 3-D FPGAs, where logic and I/O resources are assigned to different layers. Experimental results shown that such a 3-D architecture is suitable especially for communication intensive applications, since a device with two layers achieves delay reduction, as compared to conventional 2-D FPGAs up to 87% without any overhead in power dissipation. © 2011 IEEE.	en
heal.journalName	Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011	en
dc.identifier.doi	10.1109/FPL.2011.109	en
dc.identifier.spage	30	en
dc.identifier.epage	33	en