A methodology and tool framework for supporting rapid exploration of memory hierarchies in FPGAS

Sidiropoulos, H; Siozios, K; Soudris, D

dc.contributor.author	Sidiropoulos, H	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:47:14Z
dc.date.available	2014-03-01T02:47:14Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33026
dc.subject	Memory Hierarchy	en
dc.subject	Open Source	en
dc.subject.other	Critical tasks	en
dc.subject.other	Floor-planning	en
dc.subject.other	FPGA devices	en
dc.subject.other	Memory hierarchy	en
dc.subject.other	Memory organizations	en
dc.subject.other	Novel methodology	en
dc.subject.other	Open source tools	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Memory architecture	en
dc.title	A methodology and tool framework for supporting rapid exploration of memory hierarchies in FPGAS	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/FPL.2011.110	en
heal.identifier.secondary	http://dx.doi.org/10.1109/FPL.2011.110	en
heal.identifier.secondary	6044771	en
heal.publicationDate	2011	en
heal.abstract	This paper introduces a novel methodology for enabling apid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named NAROUTO. Among others, the proposed framework enables critical tasks during architecture's design, such as memory hierarchy and floor-planning. Furthermore, NAROUTO framework is the only available solution for power/energy evaluation of different memory organizations. Experimental results shown that NAROUTO framework leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions. © 2011 IEEE.	en
heal.journalName	Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011	en
dc.identifier.doi	10.1109/FPL.2011.110	en
dc.identifier.spage	238	en
dc.identifier.epage	243	en