A novel methodology for architecture-level exploration of 3D SoCs

Diamantopoulos, D; Siozios, K; Bekiaris, D; Soudris, D

dc.contributor.author	Diamantopoulos, D	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:47:14Z
dc.date.available	2014-03-01T02:47:14Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33028
dc.subject	3D IC	en
dc.subject	CAD Tools	en
dc.subject	Methodology	en
dc.subject	Physical Design	en
dc.subject.other	3-D integration	en
dc.subject.other	3D IC	en
dc.subject.other	3D technology	en
dc.subject.other	CAD Tools	en
dc.subject.other	CMOS scaling	en
dc.subject.other	Embedded processors	en
dc.subject.other	Emerging technologies	en
dc.subject.other	Methodology	en
dc.subject.other	Moore's Law	en
dc.subject.other	Novel methodology	en
dc.subject.other	Optimization goals	en
dc.subject.other	Physical Design	en
dc.subject.other	Silicon area	en
dc.subject.other	Three dimensional (3D) integration	en
dc.subject.other	Wire length	en
dc.subject.other	Design	en
dc.subject.other	Integrated control	en
dc.subject.other	Nanostructured materials	en
dc.subject.other	Nanotechnology	en
dc.subject.other	Technology	en
dc.subject.other	Three dimensional	en
dc.title	A novel methodology for architecture-level exploration of 3D SoCs	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DTIS.2011.5941425	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DTIS.2011.5941425	en
heal.identifier.secondary	5941425	en
heal.publicationDate	2011	en
heal.abstract	Three-dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues interconnect advances beyond the CMOS scaling predicted by Moore's Law, which enable new capabilities not available in 2D ICs. This paper proposes a physical design framework that enables rapid evaluation of 3D SOCs under different optimization goals. For demonstration purposes we apply the proposed framework for the 3D physical design of an embedded processor. Experimental results shown that 3D integration can alleviate the constraints posed by increased wire-length, such as power consumption, by about 20% compared to the 2D implementation. © 2011 IEEE.	en
heal.journalName	6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'11 - Technical Program	en
dc.identifier.doi	10.1109/DTIS.2011.5941425	en