A reconfigurable IP characterization technique improving high-level synthesis results

Sotiriou-Xanthopoulos, E; Koutras, I; Economakos, G; Soudris, D

dc.contributor.author	Sotiriou-Xanthopoulos, E	en
dc.contributor.author	Koutras, I	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:47:15Z
dc.date.available	2014-03-01T02:47:15Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33031
dc.subject	artificial intelligence	en
dc.subject	design automation	en
dc.subject	high level synthesis	en
dc.subject	reconfigurable architectures	en
dc.subject	runtime reconfiguration	en
dc.subject.other	Bottom up approach	en
dc.subject.other	Characterization techniques	en
dc.subject.other	Component libraries	en
dc.subject.other	Data paths	en
dc.subject.other	Data-flow graphs	en
dc.subject.other	design automation	en
dc.subject.other	Design Methodology	en
dc.subject.other	Different modes	en
dc.subject.other	Digital designs	en
dc.subject.other	DSP benchmarks	en
dc.subject.other	high level synthesis	en
dc.subject.other	New components	en
dc.subject.other	Performance Gain	en
dc.subject.other	Performance improvements	en
dc.subject.other	Re-configurable	en
dc.subject.other	reconfigurable architectures	en
dc.subject.other	Reconfigurable components	en
dc.subject.other	Reconfigurable computing	en
dc.subject.other	Reconfiguration overhead	en
dc.subject.other	Resource utilizations	en
dc.subject.other	Run time reconfiguration	en
dc.subject.other	Topdown	en
dc.subject.other	Artificial intelligence	en
dc.subject.other	Computer aided design	en
dc.subject.other	Integrated control	en
dc.subject.other	Nanostructured materials	en
dc.subject.other	Nanotechnology	en
dc.subject.other	Data flow analysis	en
dc.title	A reconfigurable IP characterization technique improving high-level synthesis results	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DTIS.2011.5941416	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DTIS.2011.5941416	en
heal.identifier.secondary	5941416	en
heal.publicationDate	2011	en
heal.abstract	Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. Usually, top-down methodologies are proposed, that start from the application's dataflow graph and try to merge different parts into the same reconfigurable component. This paper presents a bottom-up approach, that searches available RTL component libraries for primitives that can be connected in alternative ways and generate new components, with different modes of functionality. Such components, called morphable components, are designed to impose the minimum accepted area and timing overhead, without any reconfiguration overhead. The great advantage of the bottom-up approach is that it can be integrated easily with existing design methodologies and tools, offering great overall performance improvements. The results obtained with different DSP benchmarks in a high-level synthesis environment show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization. © 2011 IEEE.	en
heal.journalName	6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'11 - Technical Program	en
dc.identifier.doi	10.1109/DTIS.2011.5941416	en