A standard-cell library suite for deep-deep sub-micron CMOS technologies

Bekiaris, D; Papanikolaou, A; Stamelos, G; Soudris, D; Economakos, G; Pekmestzi, K

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Stamelos, G	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:47:15Z
dc.date.available	2014-03-01T02:47:15Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33034
dc.subject	Characterization	en
dc.subject	Standard-cell	en
dc.subject	Sub-micron	en
dc.subject.other	CMOS transistors	en
dc.subject.other	Digital system	en
dc.subject.other	Industrial tools	en
dc.subject.other	Interconnect geometry	en
dc.subject.other	Library generators	en
dc.subject.other	Nano-meter regimes	en
dc.subject.other	Nanoscale era	en
dc.subject.other	Scaling rules	en
dc.subject.other	Standard-cell	en
dc.subject.other	Sub-micron CMOS technology	en
dc.subject.other	Submicron	en
dc.subject.other	Submicron technologies	en
dc.subject.other	Technology nodes	en
dc.subject.other	VLSI system	en
dc.subject.other	CMOS integrated circuits	en
dc.subject.other	Design	en
dc.subject.other	Digital libraries	en
dc.subject.other	Electric batteries	en
dc.subject.other	Integrated control	en
dc.subject.other	Libraries	en
dc.subject.other	Microfabrication	en
dc.subject.other	Nanostructured materials	en
dc.subject.other	Nanotechnology	en
dc.subject.other	Technology	en
dc.subject.other	Standardization	en
dc.title	A standard-cell library suite for deep-deep sub-micron CMOS technologies	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DTIS.2011.5941445	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DTIS.2011.5941445	en
heal.identifier.secondary	5941445	en
heal.publicationDate	2011	en
heal.abstract	The continuous scaling of CMOS transistor and interconnect geometries brings to light novel challenges regarding the design of VLSI systems in the nanoscale era. On the other hand, most of the forthcoming deep-deep submicron technologies are not yet mature to be used for fabrication. Hence, the development of standard-cell libraries at the nanometer regime is emerging, in order to estimate the behavior of complex systems in short-term technology nodes. In this paper, we introduce a standard-cell library generator flow for sub-65nm nodes, based on scaling rules presented in the literature. Our goal is to create a set of complete standard cell libraries enabling the design of large digital systems in technologies not yet available for fabrication. The generated libraries are compatible with the state-of-the-art industrial tool flows and they have been evaluated by benchmarks of medium and large complexity. © 2011 IEEE.	en
heal.journalName	6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'11 - Technical Program	en
dc.identifier.doi	10.1109/DTIS.2011.5941445	en