dc.contributor.author |
Kouloumentas, Ch |
en |
dc.contributor.author |
Bougioukos, M |
en |
dc.contributor.author |
Spyropoulou, M |
en |
dc.contributor.author |
Klonidis, D |
en |
dc.contributor.author |
Giannoulis, G |
en |
dc.contributor.author |
Kalavrouziotis, D |
en |
dc.contributor.author |
Maziotis, A |
en |
dc.contributor.author |
Gkroumas, P |
en |
dc.contributor.author |
Apostolopoulos, D |
en |
dc.contributor.author |
Bakopoulos, P |
en |
dc.contributor.author |
Poustie, A |
en |
dc.contributor.author |
Maxwell, G |
en |
dc.contributor.author |
Velthaus, KO |
en |
dc.contributor.author |
Kaiser, R |
en |
dc.contributor.author |
Moerl, L |
en |
dc.contributor.author |
Tomkos, I |
en |
dc.contributor.author |
Avramopoulos, H |
en |
dc.date.accessioned |
2014-03-01T02:47:16Z |
|
dc.date.available |
2014-03-01T02:47:16Z |
|
dc.date.issued |
2011 |
en |
dc.identifier.issn |
21627339 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/33048 |
|
dc.subject |
advanced modulation formats |
en |
dc.subject |
hybrid integration |
en |
dc.subject |
Monolithic arrays |
en |
dc.subject |
optical regeneration |
en |
dc.subject.other |
Advanced modulation formats |
en |
dc.subject.other |
Cost-efficiency |
en |
dc.subject.other |
Data signals |
en |
dc.subject.other |
Device-scaling |
en |
dc.subject.other |
High capacity |
en |
dc.subject.other |
High yield |
en |
dc.subject.other |
Hybrid integration |
en |
dc.subject.other |
InP |
en |
dc.subject.other |
Integrated arrays |
en |
dc.subject.other |
Integration approach |
en |
dc.subject.other |
Low-power consumption |
en |
dc.subject.other |
Modulated signal |
en |
dc.subject.other |
Monolithic arrays |
en |
dc.subject.other |
Monolithic chip |
en |
dc.subject.other |
Multi-level |
en |
dc.subject.other |
Multifunctionality |
en |
dc.subject.other |
On-chip capacity |
en |
dc.subject.other |
Optical regeneration |
en |
dc.subject.other |
Roadmap |
en |
dc.subject.other |
Silica-on-silicon |
en |
dc.subject.other |
System levels |
en |
dc.subject.other |
Systems on chips |
en |
dc.subject.other |
Terabit |
en |
dc.subject.other |
WDM optical networks |
en |
dc.subject.other |
Fiber optic networks |
en |
dc.subject.other |
Microprocessor chips |
en |
dc.subject.other |
Silica |
en |
dc.subject.other |
Transparent optical networks |
en |
dc.subject.other |
Agile manufacturing systems |
en |
dc.title |
Agile photonic integrated systems-on-chip enabling WDM terabit networks |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/ICTON.2011.5971010 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/ICTON.2011.5971010 |
en |
heal.identifier.secondary |
5971010 |
en |
heal.publicationDate |
2011 |
en |
heal.abstract |
The ICT-APACHE research project is focusing on the development of cost-effective, compact, scalable and agile integrated components capable of generating, regenerating and receiving multi-level encoded data signals for high capacity (>100 Gb/s) WDM optical networks. APACHE technology relies on InP active, monolithic chips, hybridly integrated on silica-on-silicon planar lightwave platforms in order to achieve cost-efficiency, high yield, low power consumption and device scaling beyond the level commercially available today. The APACHE integration approach is implemented in a two-dimensional plan, horizontally and vertically, in order to enable multi-functionality and increased capacity, respectively. The final goal of the APACHE project is the fabrication of integrated arrays of transmitters, receivers and regenerators that will operate with 100 Gb/s OOK, DPSK and DQPSK modulated signals, allowing for 1 Terabit/s on-chip capacity. In this paper, we will review the latest results from the system-level characterization of the developed components and will outline the roadmap for future endeavours. © 2011 IEEE. |
en |
heal.journalName |
International Conference on Transparent Optical Networks |
en |
dc.identifier.doi |
10.1109/ICTON.2011.5971010 |
en |