Switch allocator for bufferless network-on-chip routers

Dimitrakopoulos, G; Galanopoulos, K

dc.contributor.author	Dimitrakopoulos, G	en
dc.contributor.author	Galanopoulos, K	en
dc.date.accessioned	2014-03-01T02:47:29Z
dc.date.available	2014-03-01T02:47:29Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33171
dc.subject	Bufferless router	en
dc.subject	Deflection routing	en
dc.subject	Logic design	en
dc.subject	Switch allocation	en
dc.subject.other	Allocators	en
dc.subject.other	Bufferless router	en
dc.subject.other	Bufferless switches	en
dc.subject.other	Clock frequency	en
dc.subject.other	Control logic	en
dc.subject.other	Deflection routing	en
dc.subject.other	Design option	en
dc.subject.other	Energy-efficient design	en
dc.subject.other	Faster implementation	en
dc.subject.other	Large delays	en
dc.subject.other	Low-latency	en
dc.subject.other	Net work utilization	en
dc.subject.other	Network on chip	en
dc.subject.other	On-chip networks	en
dc.subject.other	Switch allocation	en
dc.subject.other	Computer architecture	en
dc.subject.other	Energy efficiency	en
dc.subject.other	Interconnection networks	en
dc.subject.other	Logic design	en
dc.subject.other	Routers	en
dc.subject.other	Switching circuits	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Network architecture	en
dc.title	Switch allocator for bufferless network-on-chip routers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1930037.1930043	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1930037.1930043	en
heal.publicationDate	2011	en
heal.abstract	Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the control logic required to operate a bufferless switch that imposes large delays and limits the clock frequency. Pipelining is not an option in this low-latency environment. In this paper, we propose a new switch allocator for bufferless switches that parallelizes the steps required for achieving a match between requesting inputs and available outputs and offers significantly faster implementations. Copyright © 2011 ACM.	en
heal.journalName	ACM International Conference Proceeding Series	en
dc.identifier.doi	10.1145/1930037.1930043	en
dc.identifier.spage	19	en
dc.identifier.epage	22	en