Thermal optimization for micro-architectures through selective block replication

Diamantopoulos, D; Siozios, K; Xydis, S; Soudris, D

dc.contributor.author	Diamantopoulos, D	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:47:30Z
dc.date.available	2014-03-01T02:47:30Z
dc.date.issued	2011	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33179
dc.subject	Architectural Design	en
dc.subject	Computer Architecture	en
dc.subject	Power Density	en
dc.subject	Temperature Control	en
dc.subject	Thermal Stress	en
dc.subject	system on a chip	en
dc.subject.other	45nm technology	en
dc.subject.other	Aging phenomena	en
dc.subject.other	Architecture designs	en
dc.subject.other	Deep sub-micron technology	en
dc.subject.other	Hotspots	en
dc.subject.other	Micro architectures	en
dc.subject.other	On-chip temperature	en
dc.subject.other	Power densities	en
dc.subject.other	Resource replication	en
dc.subject.other	Silicon area	en
dc.subject.other	Temperature reduction	en
dc.subject.other	Thermal optimization	en
dc.subject.other	Computer simulation	en
dc.subject.other	Embedded systems	en
dc.subject.other	Computer architecture	en
dc.title	Thermal optimization for micro-architectures through selective block replication	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/SAMOS.2011.6045445	en
heal.identifier.secondary	http://dx.doi.org/10.1109/SAMOS.2011.6045445	en
heal.identifier.secondary	6045445	en
heal.publicationDate	2011	en
heal.abstract	Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe for deep-submicron technologies. In this paper, we propose a thermal-aware exploration framework at the microarchitecture level for temperature hotspots elimination through selective resource replication. Experimental results based on the LEON3 processor synthesized with a 45 nm technology library, shown that the proposed methodology leads to designs with fewer hotspots, while the maximal temperatures at these hotspots are also reduced. Specifically, temperature reduction of 17 Kelvin degrees is feasible, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, as compared to conventional architecture design. © 2011 IEEE.	en
heal.journalName	Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011	en
dc.identifier.doi	10.1109/SAMOS.2011.6045445	en
dc.identifier.spage	59	en
dc.identifier.epage	66	en