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BIT-PARALLEL VLSI IMPLEMENTATIONS OF RECURSIVE DIGITAL FILTERS.

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dc.contributor.author Caraiscos, Christos en
dc.contributor.author Liu, Bede en
dc.date.accessioned 2014-03-01T02:47:48Z
dc.date.available 2014-03-01T02:47:48Z
dc.date.issued 1987 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/33350
dc.relation.uri http://www.scopus.com/inward/record.url?eid=2-s2.0-0023172426&partnerID=40&md5=b7fc9ed9a9899ecf6e8b3694982053af en
dc.subject.other COMPUTERS, DIGITAL - Multiplying Circuits en
dc.subject.other INTEGRATED CIRCUITS, VLSI en
dc.subject.other MATHEMATICAL TECHNIQUES - Transfer Functions en
dc.subject.other BIT-PARALLEL ARITHMETIC en
dc.subject.other BIT-PARALLEL MULTIPLIERS en
dc.subject.other LATCHED MULTIPLIERS/ADDERS en
dc.subject.other RECURSIVE DIGITAL FILTERS en
dc.subject.other ELECTRIC FILTERS, DIGITAL en
dc.title BIT-PARALLEL VLSI IMPLEMENTATIONS OF RECURSIVE DIGITAL FILTERS. en
heal.type conferenceItem en
heal.publicationDate 1987 en
heal.abstract Schemes for direct implementation of recursive digital filters using bit-parallel arithmetic are presented. Two arrays of bit-parallel multipliers are used to realize the numerator and the denominator of the transfer functions. Latching has been introduced to the computing elements for throughput maximization. The use of latched multipliers/adders restricts the denominator polynomials to be functions of a power of z**-**1. Such filters can be designed either directly or by transforming a general transfer function into this specialized form. en
heal.publisher IEEE, New York, NY, USA en
heal.journalName [No source information available] en
dc.identifier.spage 381 en
dc.identifier.epage 384 en


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