Electrical modelling of lossy on-chip multilevel interconnecting lines

Dimopoulos, K; Avaritsiotis, J; White, S

dc.contributor.author	Dimopoulos, K	en
dc.contributor.author	Avaritsiotis, J	en
dc.contributor.author	White, S	en
dc.date.accessioned	2014-03-01T02:47:57Z
dc.date.available	2014-03-01T02:47:57Z
dc.date.issued	1991	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33465
dc.subject	High Speed	en
dc.subject	Method of Moment	en
dc.subject	Time Varying	en
dc.title	Electrical modelling of lossy on-chip multilevel interconnecting lines	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/EDAC.1991.206370	en
heal.identifier.secondary	http://dx.doi.org/10.1109/EDAC.1991.206370	en
heal.publicationDate	1991	en
heal.abstract	A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analysis	en
heal.journalName	European Design and Test Conference	en
dc.identifier.doi	10.1109/EDAC.1991.206370	en