Electrical modelling of lossy on-chip multilevel interconnecting lines

Dimopoulos, KZ; Avaritsiotis, JN; White, SJ

dc.contributor.author	Dimopoulos, KZ	en
dc.contributor.author	Avaritsiotis, JN	en
dc.contributor.author	White, SJ	en
dc.date.accessioned	2014-03-01T02:48:07Z
dc.date.available	2014-03-01T02:48:07Z
dc.date.issued	1992	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33545
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-0027045475&partnerID=40&md5=68ae3ff2f312e4d4d08cde0d10454e30	en
dc.subject.other	Computer aided design	en
dc.subject.other	Electric losses	en
dc.subject.other	Electric network topology	en
dc.subject.other	Integrated circuit layout	en
dc.subject.other	Mathematical models	en
dc.subject.other	Microprocessor chips	en
dc.subject.other	Electrical models	en
dc.subject.other	Lossy on-chip interconnecting lines	en
dc.subject.other	Method of moments	en
dc.subject.other	Multiple coupled line model	en
dc.subject.other	VLSI circuits	en
dc.title	Electrical modelling of lossy on-chip multilevel interconnecting lines	en
heal.type	conferenceItem	en
heal.publicationDate	1992	en
heal.abstract	A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analysis of coupled line systems with linear or nonlinear/time varying terminators, as well as for the study of the pulse propagation characteristics in high-speed ICs. Numerical results are presented for 3-D parallel and galvanically separated crossed planar lines.	en
heal.publisher	Publ by IEEE, Piscataway, NJ, United States	en
heal.journalName	[No source information available]	en
dc.identifier.spage	106	en
dc.identifier.epage	110	en