A Petri net approach to the design of processor array architectures

Karagianni, K; Soudris, D; Stouraitis, T

dc.contributor.author	Karagianni, K	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Stouraitis, T	en
dc.date.accessioned	2014-03-01T02:48:17Z
dc.date.available	2014-03-01T02:48:17Z
dc.date.issued	1995	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33701
dc.subject	Nested Loops	en
dc.subject	petri net	en
dc.title	A Petri net approach to the design of processor array architectures	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/MWSCAS.1995.504372	en
heal.identifier.secondary	http://dx.doi.org/10.1109/MWSCAS.1995.504372	en
heal.publicationDate	1995	en
heal.abstract	In this paper, a methodology for deriving processor array architectures that meet desired specifications for nested-loop algorithms is introduced. The methodology is based upon the construction of a Petri net model for the dependencies of the algorithm, the development of a forest of reachability trees for this model and the creation of an execution graph. Different executions of the algorithm	en
heal.journalName	Midwest Symposium on Circuits and Systems	en
dc.identifier.doi	10.1109/MWSCAS.1995.504372	en