Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment

Economakos, G; Papakonstantinou, G

dc.contributor.author	Economakos, G	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:48:36Z
dc.date.available	2014-03-01T02:48:36Z
dc.date.issued	1998	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/33954
dc.subject	Attribute Grammar	en
dc.subject	Experimental Tests	en
dc.subject	High Level Synthesis	en
dc.subject	Technology Mapping	en
dc.title	Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/EURMIC.1998.711782	en
heal.identifier.secondary	http://dx.doi.org/10.1109/EURMIC.1998.711782	en
heal.publicationDate	1998	en
heal.abstract	Recently, the AGENDA formal framework to perform high-level synthesis using attribute grammars has been presented, its main advantages being modularity and declarative notation in the development of EDA environments. To integrate this framework with modern optimization and technology mapping tools, compliance with the corresponding design entry method is needed. This paper gives a brief overview of AGENDA, focuses on different	en
heal.journalName	Conference on Software Engineering and Advanced Applications	en
dc.identifier.doi	10.1109/EURMIC.1998.711782	en