A novel architecture for efficient protocol processing in high speed communication environments

KONSTANTOULAKIS, G; NELLAS, V; GEORGOPOULOS, C; ORPHANOUDAKIS, T; ZERVOS, N; STECK, M; Verkest, D; DOUMENIS, G; Reisis, D; Nikolaou, N; Sanchez, J

dc.contributor.author	KONSTANTOULAKIS, G	en
dc.contributor.author	NELLAS, V	en
dc.contributor.author	GEORGOPOULOS, C	en
dc.contributor.author	ORPHANOUDAKIS, T	en
dc.contributor.author	ZERVOS, N	en
dc.contributor.author	STECK, M	en
dc.contributor.author	Verkest, D	en
dc.contributor.author	DOUMENIS, G	en
dc.contributor.author	Reisis, D	en
dc.contributor.author	Nikolaou, N	en
dc.contributor.author	Sanchez, J	en
dc.date.accessioned	2014-03-01T02:48:51Z
dc.date.available	2014-03-01T02:48:51Z
dc.date.issued	2000	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34116
dc.subject	High Performance	en
dc.subject	High Speed	en
dc.subject	Transport Protocol	en
dc.subject	Hard Real Time	en
dc.title	A novel architecture for efficient protocol processing in high speed communication environments	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ECUMN.2000.880794	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ECUMN.2000.880794	en
heal.publicationDate	2000	en
heal.abstract	The architecture, system modules and functional design of a reconfigurable protocol processor are presented. The protocol processor aims in accelerating execution of telecom transport protocols by extending a high-performance RISC core with reconfigurable pipelined hardware. CPU demanding and (hard) real-time protocol functions will be handled by the programmable hardware, while the remaining functions as well as higher layer protocols will	en
heal.journalName	European Conference on Universal Multiservice Networks	en
dc.identifier.doi	10.1109/ECUMN.2000.880794	en