A Multi-Lingual Synthesis and Verification Environment

Economakos, G; Stergiou, S; Papakonstantinou, G; Zoukos, V

dc.contributor.author	Economakos, G	en
dc.contributor.author	Stergiou, S	en
dc.contributor.author	Papakonstantinou, G	en
dc.contributor.author	Zoukos, V	en
dc.date.accessioned	2014-03-01T02:49:02Z
dc.date.available	2014-03-01T02:49:02Z
dc.date.issued	2001	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34238
dc.subject	Design Environment	en
dc.subject	Design Management	en
dc.subject	Hardware Description Language	en
dc.subject	Low Complexity	en
dc.subject	Spectrum	en
dc.title	A Multi-Lingual Synthesis and Verification Environment	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DSD.2001.952111	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DSD.2001.952111	en
heal.publicationDate	2001	en
heal.abstract	The adoption of hardware description languages as a de- sign speciJication formalism, in the electronic design au- tomation industry, has reached acceptance during the last years. This effort has been mainly supported by the VHDL and Verilog standardization activities, which are now of- fering a common formalism among different tool vendors, as well as novel ideas like the SystemC C++	en
heal.journalName	Euromicro Symposium on Digital Systems Design	en
dc.identifier.doi	10.1109/DSD.2001.952111	en