The architecture design for a terabit IP switch router

Yang, J; Uzan, N; Papavassiliou, S

dc.contributor.author	Yang, J	en
dc.contributor.author	Uzan, N	en
dc.contributor.author	Papavassiliou, S	en
dc.date.accessioned	2014-03-01T02:49:06Z
dc.date.available	2014-03-01T02:49:06Z
dc.date.issued	2001	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34299
dc.subject	Architectural Design	en
dc.subject	High Speed	en
dc.subject	Packet Switched	en
dc.title	The architecture design for a terabit IP switch router	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/HPSR.2001.923661	en
heal.identifier.secondary	http://dx.doi.org/10.1109/HPSR.2001.923661	en
heal.publicationDate	2001	en
heal.abstract	We propose an architecture for scalable, high capacity IP switch routers in which we apply fixed-length packet switching technology to support high speed IP forwarding. The proposed IP switch router consists of routing controllers, routing modules and a switch plane. The architectures of routing modules and switch plane whose aggregate capacity can be as large as ten terabit are proposed.	en
heal.journalName	IEEE Workshop on High Performance Switching and Routing	en
dc.identifier.doi	10.1109/HPSR.2001.923661	en