A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping

Athanasaki, M; Sotiropoulos, A; Tsoukalas, G; Koziris, N

dc.contributor.author	Athanasaki, M	en
dc.contributor.author	Sotiropoulos, A	en
dc.contributor.author	Tsoukalas, G	en
dc.contributor.author	Koziris, N	en
dc.date.accessioned	2014-03-01T02:49:07Z
dc.date.available	2014-03-01T02:49:07Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34319
dc.subject	Nested Loops	en
dc.subject	Network Interface Card	en
dc.title	A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICPPW.2002.1039778	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICPPW.2002.1039778	en
heal.publicationDate	2002	en
heal.abstract	This paper proposes a novel approach for the parallel execution of tiled Iteration Spaces onto a cluster of SMP PC nodes. Each SMP node has multiple CPUs and a sin- gle memory mapped PCI-SCI Network Interface Card. We apply a hyperplane-based grouping transformation to the tiled space, so as to group together independent neighbor- ing tiles and assign them to	en
heal.journalName	International Conference on Parallel Processing	en
dc.identifier.doi	10.1109/ICPPW.2002.1039778	en