Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id

Foty, D; Bucher, M; Binkley, D

dc.contributor.author	Foty, D	en
dc.contributor.author	Bucher, M	en
dc.contributor.author	Binkley, D	en
dc.date.accessioned	2014-03-01T02:49:16Z
dc.date.available	2014-03-01T02:49:16Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34455
dc.subject.other	Analog CMOS	en
dc.subject.other	Device currents	en
dc.subject.other	Inversion coefficient	en
dc.subject.other	MOS transistors	en
dc.subject.other	Proper models	en
dc.subject.other	Weak inversions	en
dc.subject.other	Transistor transistor logic circuits	en
dc.title	Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2002.1046463	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2002.1046463	en
heal.identifier.secondary	1046463	en
heal.publicationDate	2002	en
heal.abstract	A method of interpreting MOS transistor behavior is described which is simple yet fundamental and universal. Device currents are normalized to the inversion coefficient (IC) and interpreted via gms/Id Measurements confirm this behavior, and demonstrate the need for the development of proper model forms for usage of this description, This interpretation also connects directly with modern analog CMOS design needs, allowing for the positive use of moderate and weak inversion, in a manner which permits a coherent evolution of a design toward the final goals. © 2002 IEEE.	en
heal.journalName	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems	en
dc.identifier.doi	10.1109/ICECS.2002.1046463	en
dc.identifier.volume	3	en
dc.identifier.spage	1179	en
dc.identifier.epage	1182	en