FPGA Architecture Design and Toolset for Logic Implementation

Tatas, K; Siozios, K; Vassiliadis, N; Soudris, D; Nikolaidis, S; Siskos, S; Thanailakis, A

dc.contributor.author	Tatas, K	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Vassiliadis, N	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Nikolaidis, S	en
dc.contributor.author	Siskos, S	en
dc.contributor.author	Thanailakis, A	en
dc.date.accessioned	2014-03-01T02:49:19Z
dc.date.available	2014-03-01T02:49:19Z
dc.date.issued	2003	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34509
dc.subject	Design Flow	en
dc.subject	Design Support	en
dc.subject	Energy Consumption	en
dc.subject	fpga architecture	en
dc.subject	Interconnection Network	en
dc.subject	Tool Support	en
dc.subject	configurable logic block	en
dc.title	FPGA Architecture Design and Toolset for Logic Implementation	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-540-39762-5_67	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-540-39762-5_67	en
heal.publicationDate	2003	en
heal.abstract	In this paper, the design of an embedded FPGA architecture (i.e. configurable logic blocks) is presented and a complete tool-supported design flow starting from architecture level (i.e. RT-level) and ending with the derivation of the reconfiguration bitstream for the FPGA programming is introduced. The proposed design flow consists of new and modified and extended academic tools. In particular, new tools	en
heal.journalName	Workshop on Power and Timing Modeling, Optimization and Simulation	en
dc.identifier.doi	10.1007/978-3-540-39762-5_67	en