Global interconnect trade-off for technology over memory modules to application level: case study

Papanikolaou, A; Miranda, M; Catthoor, F; Corporaal, H; Man, H; Roest, D; Stucchi, M; Maex, K

dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Catthoor, F	en
dc.contributor.author	Corporaal, H	en
dc.contributor.author	Man, H	en
dc.contributor.author	Roest, D	en
dc.contributor.author	Stucchi, M	en
dc.contributor.author	Maex, K	en
dc.date.accessioned	2014-03-01T02:49:19Z
dc.date.available	2014-03-01T02:49:19Z
dc.date.issued	2003	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34513
dc.subject	Case Study	en
dc.subject	pareto optimality	en
dc.subject	Power Consumption	en
dc.subject	Real Time	en
dc.title	Global interconnect trade-off for technology over memory modules to application level: case study	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/639929.639954	en
heal.identifier.secondary	http://dx.doi.org/10.1145/639929.639954	en
heal.publicationDate	2003	en
heal.abstract	In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach	en
heal.journalName	System-Level Interconnect Prediction	en
dc.identifier.doi	10.1145/639929.639954	en