Processing and Scheduling Components in an Innovative Network Processor Architecture

Vlachos, K; Nikolaou, N; Orphanoudakis, T; Perissakis, S; Pnevmatikatos, D; Kornaros, G; Sanchez, J; Konstantoulakis, G

dc.contributor.author	Vlachos, K	en
dc.contributor.author	Nikolaou, N	en
dc.contributor.author	Orphanoudakis, T	en
dc.contributor.author	Perissakis, S	en
dc.contributor.author	Pnevmatikatos, D	en
dc.contributor.author	Kornaros, G	en
dc.contributor.author	Sanchez, J	en
dc.contributor.author	Konstantoulakis, G	en
dc.date.accessioned	2014-03-01T02:49:21Z
dc.date.available	2014-03-01T02:49:21Z
dc.date.issued	2003	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34535
dc.subject	High Speed Networks	en
dc.subject	Innovation Network	en
dc.subject	Processor Architecture	en
dc.subject	Resource Manager	en
dc.subject	Tight Coupling	en
dc.subject	Traffic Shaping	en
dc.title	Processing and Scheduling Components in an Innovative Network Processor Architecture	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICVD.2003.1183136	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICVD.2003.1183136	en
heal.publicationDate	2003	en
heal.abstract	In this paper, we describe the architecture of an innovative network processor aiming at the acceleration of packet processing in high speed network interfaces and at the tight coupling of low and high level protocols. The proposed design uses programmable hard-wired components with line rate throughput and is capable of executing protocols and handling efficiently high and low level streaming	en
heal.journalName	VLSI Design	en
dc.identifier.doi	10.1109/ICVD.2003.1183136	en