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Hardware implementation of syntactic pattern recognition algorithms

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dc.contributor.author Pavlatos, C en
dc.contributor.author Koulouris, A en
dc.contributor.author Papakonstantinou, G en
dc.date.accessioned 2014-03-01T02:49:24Z
dc.date.available 2014-03-01T02:49:24Z
dc.date.issued 2003 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/34583
dc.relation.uri http://www.scopus.com/inward/record.url?eid=2-s2.0-1542538533&partnerID=40&md5=fcf4b51bfcaaf8c5128ab447678f9b7c en
dc.subject Attribute grammars (AG) en
dc.subject Barley's algorithm en
dc.subject Context-free grammars (CFG) en
dc.subject Parallel parsing en
dc.subject.other Algorithms en
dc.subject.other Computational complexity en
dc.subject.other Computer hardware en
dc.subject.other Dynamic programming en
dc.subject.other Set theory en
dc.subject.other Attribute grammars (AG) en
dc.subject.other Context-free grammars (CFG) en
dc.subject.other Earley algorithms en
dc.subject.other Parallel parsing en
dc.subject.other Pattern recognition en
dc.title Hardware implementation of syntactic pattern recognition algorithms en
heal.type conferenceItem en
heal.publicationDate 2003 en
heal.abstract Syntactic pattern recognition is of great importance to a considerable number of applications. Attribute Grammars have extensively been used for syntactic pattern recognition applications. In this paper a methodology is proposed for the hardware implementation of parallel Earley's algorithm augmented with attributes and semantic rules so that one pass (from left to right) attribute grammars evaluators can be implemented in hardware. Finally an illustrative example is given for the analysis of a waveform. en
heal.journalName Proceedings of the IASTED International Conference on Signal Processing, Pattern Reconition, and Applications en
dc.identifier.spage 360 en
dc.identifier.epage 365 en


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