Scheduling components for multi-gigabit network SoCs

Orphanoudakis, T; Kornaros, G; Papaefstathiou, I; Leligou, H-C; Perissakis, S; Zervos, N

dc.contributor.author	Orphanoudakis, T	en
dc.contributor.author	Kornaros, G	en
dc.contributor.author	Papaefstathiou, I	en
dc.contributor.author	Leligou, H-C	en
dc.contributor.author	Perissakis, S	en
dc.contributor.author	Zervos, N	en
dc.date.accessioned	2014-03-01T02:49:35Z
dc.date.available	2014-03-01T02:49:35Z
dc.date.issued	2003	en
dc.identifier.issn	0277786X	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34625
dc.subject	Network processor	en
dc.subject	Programmable hardware	en
dc.subject	Scheduling	en
dc.subject	SoC	en
dc.subject.other	Algorithms	en
dc.subject.other	Computer hardware	en
dc.subject.other	Data communication systems	en
dc.subject.other	Network protocols	en
dc.subject.other	Reduced instruction set computing	en
dc.subject.other	Scheduling	en
dc.subject.other	Telecommunication control	en
dc.subject.other	Telecommunication networks	en
dc.subject.other	Telecommunication traffic	en
dc.subject.other	Network processor	en
dc.subject.other	Protocol Programmable Processor	en
dc.subject.other	Systems-on-chip	en
dc.subject.other	Microprocessor chips	en
dc.title	Scheduling components for multi-gigabit network SoCs	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1117/12.498488	en
heal.identifier.secondary	http://dx.doi.org/10.1117/12.498488	en
heal.publicationDate	2003	en
heal.abstract	To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor (PRO3) that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PRO3 is, in general, crucial for network Systems-on-Chip (SoCs) since it makes it feasible to use external memories for scheduling and still accommodate multi-gigabit network speeds. Extensions to the PRO3 scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.	en
heal.journalName	Proceedings of SPIE - The International Society for Optical Engineering	en
dc.identifier.doi	10.1117/12.498488	en
dc.identifier.volume	5117	en
dc.identifier.spage	86	en
dc.identifier.epage	97	en