A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

Haralabidis, N; Vavelidis, K; Vassiliou, I; Georgantas, T; Yamanaka, A; Kavadias, S; Kamoulakos, G; Kapnistis, C; Kokolakis, Y; Kyranas, A; Merakos, P; Bouras, I; Bouras, S; Plevridis, S

dc.contributor.author	Haralabidis, N	en
dc.contributor.author	Vavelidis, K	en
dc.contributor.author	Vassiliou, I	en
dc.contributor.author	Georgantas, T	en
dc.contributor.author	Yamanaka, A	en
dc.contributor.author	Kavadias, S	en
dc.contributor.author	Kamoulakos, G	en
dc.contributor.author	Kapnistis, C	en
dc.contributor.author	Kokolakis, Y	en
dc.contributor.author	Kyranas, A	en
dc.contributor.author	Merakos, P	en
dc.contributor.author	Bouras, I	en
dc.contributor.author	Bouras, S	en
dc.contributor.author	Plevridis, S	en
dc.date.accessioned	2014-03-01T02:49:37Z
dc.date.available	2014-03-01T02:49:37Z
dc.date.issued	2004	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34644
dc.subject	Analog Circuits	en
dc.subject	Cost Efficiency	en
dc.subject	Innovation System	en
dc.subject	Phase Noise	en
dc.subject	Wireless Lan	en
dc.title	A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/CICC.2004.1358834	en
heal.identifier.secondary	http://dx.doi.org/10.1109/CICC.2004.1358834	en
heal.publicationDate	2004	en
heal.abstract	A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 μm CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on	en
heal.journalName	Custom Integrated Circuits Conference	en
dc.identifier.doi	10.1109/CICC.2004.1358834	en