An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development

Kalenteridis, V; Pournara, H; Siozios, K; Tatas, K; Koutroumpezis, G; Pappas, I; Nikolaidis, S; Siskos, S; Soudris, D; Thanailakis, A

dc.contributor.author	Kalenteridis, V	en
dc.contributor.author	Pournara, H	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Tatas, K	en
dc.contributor.author	Koutroumpezis, G	en
dc.contributor.author	Pappas, I	en
dc.contributor.author	Nikolaidis, S	en
dc.contributor.author	Siskos, S	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Thanailakis, A	en
dc.date.accessioned	2014-03-01T02:49:38Z
dc.date.available	2014-03-01T02:49:38Z
dc.date.issued	2004	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34652
dc.subject	Design Framework	en
dc.subject	Digital Logic	en
dc.subject	Energy Efficient	en
dc.subject	fpga architecture	en
dc.subject	Graphic User Interface	en
dc.subject	Low Power	en
dc.subject	reconfigurable hardware	en
dc.title	An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IPDPS.2004.1303112	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IPDPS.2004.1303112	en
heal.publicationDate	2004	en
heal.abstract	A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18µm	en
heal.journalName	International Parallel and Distributed Processing Symposium/International Parallel Processing Symposium	en
dc.identifier.doi	10.1109/IPDPS.2004.1303112	en