Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform

Masselos, K; Blionas, S; Mignolet, J; Foster, A; Soudris, D; Nikolaidis, S

dc.contributor.author	Masselos, K	en
dc.contributor.author	Blionas, S	en
dc.contributor.author	Mignolet, J	en
dc.contributor.author	Foster, A	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Nikolaidis, S	en
dc.date.accessioned	2014-03-01T02:49:38Z
dc.date.available	2014-03-01T02:49:38Z
dc.date.issued	2004	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34662
dc.subject	Building Block	en
dc.subject	Coarse Grained	en
dc.subject	Interconnection Network	en
dc.subject	reconfigurable system	en
dc.subject	Wireless Communication Systems	en
dc.subject	Wireless Network	en
dc.title	Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-540-30205-6_63	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-540-30205-6_63	en
heal.publicationDate	2004	en
heal.abstract	Abstract. Due to the combination of flexibility and realization efficiency, re- configurable hardware,has become,a promising,implementation,alternative. In the context of the IST-AMDREL project, a mixed granularity reconfigurable SoC platform targeting wireless communication ,systems has been developed. The platform’s main building blocks are presented, including coarse grain re- configurable unit, embedded FPGA, interconnection network and application specific reusable blocks. The combination,of these	en
heal.journalName	Workshop on Power and Timing Modeling, Optimization and Simulation	en
dc.identifier.doi	10.1007/978-3-540-30205-6_63	en