Small scale prototype of a CdTe imaging system

Lambropoulos, H; Papadakis, I; Loukas, D; Zervakis, M

dc.contributor.author	Lambropoulos, H	en
dc.contributor.author	Papadakis, I	en
dc.contributor.author	Loukas, D	en
dc.contributor.author	Zervakis, M	en
dc.date.accessioned	2014-03-01T02:49:55Z
dc.date.available	2014-03-01T02:49:55Z
dc.date.issued	2004	en
dc.identifier.issn	10957863	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34782
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-23844488448&partnerID=40&md5=89dd66090e3e0327631c6dd4ef2724c2	en
dc.subject.other	Amplifiers (electronic)	en
dc.subject.other	Application specific integrated circuits	en
dc.subject.other	Control equipment	en
dc.subject.other	Data acquisition	en
dc.subject.other	Data transfer	en
dc.subject.other	Discriminators	en
dc.subject.other	Electric potential	en
dc.subject.other	Interfaces (computer)	en
dc.subject.other	Radiation detectors	en
dc.subject.other	Semiconducting cadmium telluride	en
dc.subject.other	Software engineering	en
dc.subject.other	Large scale imaging instruments	en
dc.subject.other	Motherboard	en
dc.subject.other	Multichannel analyzers	en
dc.subject.other	X-ray imaging	en
dc.subject.other	Imaging systems	en
dc.title	Small scale prototype of a CdTe imaging system	en
heal.type	conferenceItem	en
heal.publicationDate	2004	en
heal.abstract	We have designed a system for data acquisition from CdTe detectors. The system incorporates a USB2 interface motherboard, a shielded daughterboard which can be piggy-back connected to the previous one and Lab view libraries. On the shielded board one can connect either a CdTe detector or a test capacitor. This board houses a mixed - signal ASIC containing various front-end readout architectures with and without discriminators and a wideband commercial amplifier, which amplifies further the output of one readout chain and brings it to the levels required by multichannel analyzers. The USB2 interface card contains a digital ASIC with 32 20-bit counters accepting signals from the discriminators, an FPGA which interfaces the 20-bit bus of the digital ASIC to the 16-bit bus of the USB controller, the USB controller which coordinates the high speed (480Mbps) data transfer to the PC and controls the programmable current and voltage sources implemented on this board and used for the bias of the mixed-signal ASIC and for setting the thresholds of the discriminators. The Labview libraries contain the VIs required for the control a) of the data transfer to and from the PC and b) of the programmable sources. The system serves our need to evaluate the performance of the combined CdTe detectors and readout ASIC towards the implementation of a large scale imaging instrument for luggage inspection. © 2004 IEEE.	en
heal.journalName	IEEE Nuclear Science Symposium Conference Record	en
dc.identifier.volume	7	en
dc.identifier.spage	4540	en
dc.identifier.epage	4542	en