A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

Papanikolaou, A; Lobmaier, F; Wang, H; Miranda, M; Catthoor, F

dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Lobmaier, F	en
dc.contributor.author	Wang, H	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T02:49:56Z
dc.date.available	2014-03-01T02:49:56Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/34805
dc.subject	Design Process	en
dc.subject	New Technology	en
dc.subject	Statistical Timing Analysis	en
dc.title	A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1084834.1084866	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1084834.1084866	en
heal.publicationDate	2005	en
heal.abstract	Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to	en
heal.journalName	International Conference on Hardware/Software Codesign and System Synthesis	en
dc.identifier.doi	10.1145/1084834.1084866	en